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US 10,872,662 B2Granted
2T2R binary weight cell with high on/off ratio background
AssigneeSamsung Electronics Co., Ltd.
InventorsRyan M. Hatcher, Titash Rakshit, Jorge Kittl, Rwik Sengupta, Dharmendar Palle, Joon Goo Hong
Life of this patent
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Abstract
A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, and a second FET and a second resistive memory element connected to a drain of the second FET. The drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET.
Claims20
A weight cell, comprising:
- a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET;
- and
- a second FET and a second resistive memory element connected to a drain of the second FET,
- wherein the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and wherein a source of the first FET is connected to a first output line and a source of the second FET is connected to a second output line.
1 more element
A device, comprising:
- an array of weight cells, each weight cell including:
- a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET;
- and
- a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET being connected to a gate of the first FET;
- and
- a processor configured to perform inference with the array of weight cells by:
- setting inputs for a row of weight cells from among the array of weight cells according to a logical value of a corresponding neuron;
- and
- reading outputs of a column of weight cells from among the array of weight cells.
6 more elements
A device, comprising:
- an array of weight cells, each weight cell including:
- a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET;
- and
- a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET being connected to a gate of the first FET;
- and
- a processor configured to write to the resistive memory elements according to a direction of a current supplied to the resistive memory elements.
3 more elements
Dependencies are inferred from the claim text.