Memory system having write assist circuit including memory-adapted transistors

A memory system comprising:

• a first array of memory cells arranged into first rows;
• a second array of write assist circuits arranged into second rows;
• the first array of memory cells and the second array of write assist circuits being arranged into columns;
• each column including a bit line and a bit_bar line operatively coupled to corresponding memory cells of the first array and a corresponding at least one write assist circuit of the second array;
• and
• each write assist circuit including:
• a first PMOS transistor and a first NMOS transistor connected in series between a power-supply voltage and a first node, gate electrodes of the first PMOS transistor and the first NMOS transistor being connected to a second node, the second node being connected to a data_bar line;
• a first switchable conductive path between the first node and a ground voltage;
• a second PMOS transistor and a second NMOS transistor connected in series between the power-supply voltage and a third node, gate electrodes of the second PMOS transistor and the second NMOS transistor being connected to a fourth node, the fourth node being connected to a data line;
• a second switchable conductive path between the third node and the ground voltage;
• a third NMOS transistor having a high resistance configuration and for which a first drain/source electrode is connected to the fourth node;
• a first shunt connecting the fourth node and the data line;
• a fourth NMOS transistor having a high resistance configuration and for which a first drain/source electrode is connected to the second node;
• and
• a second shunt connecting the second node and the data_bar line.

A memory system comprising:

• a first array of memory cells arranged into first rows;
• a second array of write assist circuits arranged into second rows;
• the first array of memory cells and the second array of write assist circuits being arranged into columns;
• each column including a bit line and a bit_bar line operatively coupled to corresponding memory cells of the first array and a corresponding at least one write assist circuit of the second array;
• and
• each write assist circuit including:
• a memory-adapted latch including:
• a memory-adapted first PMOS transistor and a memory-adapted first NMOS transistor connected in series between a power-supply voltage and a first node, the first node being selectively connectable to a ground voltage;
• and
• a memory-adapted second PMOS transistor and a memory-adapted second NMOS transistor connected in series between the power-supply voltage and a second node, the second node being selectively connectable to the ground voltage;
• a memory-adapted third NMOS transistor connected in series between the first node and the ground voltage;
• and
• a memory-adapted fourth NMOS transistor connected in series between the second node and the ground voltage;
• wherein a gate electrode of each of the memory-adapted third and fourth transistors is connected to a latch-enable signal-line thereby for controlling the memory-adapted latch;
• wherein the memory-adapted first and second PMOS and the memory-adapted first and second NMOS transistors are adapted for at least one of a memory power-domain, higher threshold voltages, lower saturation currents or lower leakage currents;
• and
• whereas logic-adapted transistors are adapted for at least one of a logic power-domain, lower threshold voltages, higher saturation currents or higher leakage currents.