Integrated circuit and memory
AssigneeSK hynix Inc.
InventorJeong-Jik Na
Life of this patent
Estimating the term…
Abstract
An integrated circuit may include an amplifier circuit configured to receive a pull-up voltage in response to a pull-up enable signal, receive a pull-down voltage in response to a pull-down enable signal, and amplify a voltage difference between a first line and a second line through the pull-up and pull-down voltages; a first delay path configured to generate the pull-up enable signal by delaying an input signal; and a second delay path configured to generate the pull-down enable signal by delaying the input signal, wherein a change in a delay of the first delay path due to variation of a power supply voltage is smaller than a change in a delay of the second delay path due to the variation.
Claims15
An integrated circuit comprising:
- an amplifier circuit configured to receive a pull-up voltage in response to a pull-up enable signal, receive a pull-down voltage in response to a pull-down enable signal, and amplify a voltage difference between a first line and a second line through the pull-up and pull-down voltages;
- a first delay path configured to generate the pull-up enable signal by delaying an input signal;
- and
- a second delay path configured to generate the pull-down enable signal by delaying the input signal,
- wherein a change in a delay of the first delay path due to variation of a power supply voltage is smaller than a change in a delay of the second delay path due to the variation.
A memory comprising:
- a bit line sense amplifier configured to receive a pull-up voltage in response to a pull-up enable signal, receive a pull-down voltage in response to a pull-down enable signal, and amplify a voltage difference between a bit line and a bit line bar through the pull-up and pull-down voltages;
- and
- an enable signal generation circuit configured to generate the pull-up enable signal and the pull-down enable signal, and to activate the pull-up enable signal earlier than the pull-down enable signal as a power supply voltage decreases.
An integrated circuit comprising:
- an amplifier circuit configured to pull-up a voltage of a first line in response to a pull-up enable signal and pull-down a voltage of a second line in response to a pull-down enable signal;
- a delay control circuit configured to generate the pull-up and pull-down enable signals by delaying a reference signal by first and second delays, respectively,
- wherein the first delay is less than the second delay, and
- wherein a difference between the first and second delays varies inversely with respect to variation of a power supply voltage.
Dependencies are inferred from the claim text.