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US 10,872,645 B1Granted
Semiconductor devices
AssigneeSK hynix Inc.
InventorsGeun Ho Choi, Kyung Mook Kim, Woongrae Kim
Life of this patent
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Abstract
A semiconductor device includes a variable delay circuit and an address latch circuit. The variable delay circuit delays a read signal by a delay time to generate a latch control signal during an initialization operation and receives a feedback signal to adjust the delay time for delaying the read signal during the initialization operation. The address latch circuit detects a logic level of a transfer address when the latch control signal is inputted to the address latch circuit and generates the feedback signal.
Claims24
A semiconductor device comprising:
- a variable delay circuit configured to delay a read signal by a delay time to generate a latch control signal during an initialization operation and configured to receive a feedback signal to adjust the delay time for delaying the read signal during the initialization operation;
- and
- an address latch circuit configured to detect a logic level of a transfer address when the latch control signal is inputted to the address latch circuit and configured to generate the feedback signal.
A semiconductor device comprising:
- a training control circuit configured to generate a read signal from a first internal read signal and a second internal read signal and configured to generate a transfer address from a test mode signal and the first and second internal read signals during an initialization operation;
- a variable delay circuit configured to delay the read signal to generate a latch control signal and configured to receive a feedback signal to adjust a delay time for delaying the read signal;
- and
- an address latch circuit configured to detect a logic level of the transfer address when the latch control signal is inputted to the address latch circuit and configured to generate the feedback signal.
1 more element
Dependencies are inferred from the claim text.