Systems and methods for a centralized command address input buffer
AssigneeMicron Technology, Inc.
InventorsYutaka Uemura, Yasuhiro Takai
Life of this patent
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Abstract
An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time.
Claims21
An apparatus comprising:
- a first pad;
- and
- a first input circuit coupled to the first pad via an input buffer, wherein the first input circuit comprises:
- a first signal propagation path coupled to the first pad;
- a latch circuit;
- a second signal propagation path coupled to the latch circuit;
- and
- a gate circuit between the first and second signal propagation paths, wherein the first signal propagation path is configured to have first signal propagation time and the second signal propagation path is configured to have second signal propagation time that is greater than the first signal propagation time.
A memory device comprising:
- a first pad;
- and
- a first input circuit coupled to the first pad, wherein the first input circuit comprises:
- a first delay block coupled to the first pad;
- a second delay block coupled to output circuitry of the first input circuit;
- and
- a gate circuit coupled between the first and second delay blocks, wherein the first delay block is configured to contribute to a first signal propagation time and the second delay block is configured to contribute to a second signal propagation time, and wherein the second delay block consumes power in response to a second pad receiving a chip select signal.
A memory device, comprising:
- one or more pads;
- and
- one or more input circuits respectively coupled to respective pads of the one or more pads, wherein each of the input circuits comprises:
- a first group of inverting logic gates coupled to a respective pad of the one or more pads;
- a latch circuit;
- a second group of inverting logic gates coupled to the latch circuit;
- and
- a gate circuit coupled to an output from the first group of inverting logic gates, wherein an output from the gate circuit is coupled to an input of the second group of inverting logic gates, wherein the first group of inverting logic gates are configured to less signal delay than the second group of inverting logic gates.
Dependencies are inferred from the claim text.