System comprising a memory capable of implementing calculation operations

A memory circuit comprising:

• a plurality of elementary storage cells arranged in an array of rows and of columns;
• a data input/output port;
• an address input port different from the data input/output;
• a mode selection input port;
• and
• an internal control circuit configured to:
• read a mode selection signal applied to the mode selection port;
• when the mode selection signal is in a first state, read an address of a row from the address input port and implement, via the data input/output port, a read or write operation in this row;
• and
• when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation comprising the simultaneous activation in read or write mode of at least two rows selected according to the instruction signal,
• wherein the instruction signal comprises a first field defining a type of operation to be implemented by the internal control circuit, wherein the internal control circuit is capable of, when the mode selection signal is in the second state, implementing a calculation operation comprising the simultaneous activation in read mode of at least two rows selected according to the instruction signal, and wherein the internal control circuit is further configured to, when the mode selection signal is in the second state, read an address signal from the address input port and write at the corresponding address of the memory circuit a result of the calculation operation.