Nwell and subtrate taps in memory layout

A circuit comprising:

• a repeating series of first circuits extending along a first direction in which the first circuits are repeated;
• a repeating series of second circuits placed next to the repeating series of first circuits and formed along diffusion regions and wells which extend in the first direction, the second circuits interacting with corresponding portions of the first circuits;
• and
• a dummy circuit region interrupting the repeating series of second circuits and the repeating series of first circuits at an interior location along each series with pluralities of the first and second circuits before and after the interior location along each respective series, the dummy circuit region not including a functioning instance of the first or second circuits, and including taps tying the diffusion regions and wells to power supply voltages.

A method comprising:

• operating a repeating series of first circuits extending along a first direction in which the first circuits are repeated;
• operating a repeating series of second circuits placed next to the repeating series of first circuits, the second circuits interacting with corresponding portions of the first circuits;
• and
• at a dummy circuit region which interrupts the repeating series of first circuits and the repeating series of second circuits at an interior location along each series with pluralities of the first and second circuits before and after the interior location along each respective series, biasing diffusion regions and wells which extend in the first direction, the diffusion regions biased to power supply voltages.