Shift register unit and driving method thereof, scan drive circuit and display apparatus

A scan drive circuit, comprising at least one shift register unit, the shift register unit comprising an input terminal and an output terminal, and further comprising an input circuit, an output control circuit, a reset control circuit and an output circuit;

• wherein
• the input circuit is connected to a first clock signal terminal, the input terminal and a first node, and configured to provide an input signal from the input terminal for the first node when a first clock signal from the first clock signal terminal is at a second level;
• the output control circuit is connected to the first clock signal terminal, a second clock signal terminal, a first level voltage line, the first node and a second node, and configured to provide a second clock signal from the second clock signal terminal for the second node when the first node is at the second level, and provide a first level from the first level voltage line for the second node when the first clock signal is at the second level;
• the reset control circuit is connected to the first clock signal terminal, the second clock signal terminal, the first level voltage line, a second level voltage line, the first node and a third node, and configured to provide the first level from the first level voltage line for the third node when the second clock signal and the first node are both at the second level, and provide a second level from the second level voltage line for the third node when the first clock signal is at the second level;
• and
• the output circuit is connected to the first level voltage line, the second level voltage line, the second node, the third node and the output terminal, and configured to provide the second level from the second level voltage line for the output terminal when the second node is at the second level, and provide the first level from the first level voltage line for the output terminal when the third node is at the second level.

A method for driving a shift register unit, wherein the method is for driving a shift register unit, the method comprising:

• at a charging stage, during which a first clock signal is at a second level, a second clock signal is at a first level, providing the second level for an input terminal of the shift register unit;
• wherein the shift register unit comprises an input terminal and an output terminal, and further comprises an input circuit, an output control circuit, a reset control circuit and an output circuit;
• wherein
• the input circuit is connected to a first clock signal terminal, the input terminal and a first node, and configured to provide an input signal from the input terminal for the first node when a first clock signal from the first clock signal terminal is at the second level;
• the output control circuit is connected to the first clock signal terminal, a second clock signal terminal, a first level voltage line, the first node and a second node, and configured to provide a second clock signal from the second clock signal terminal for the second node when the first node is at the second level, and provide a first level from the first level voltage line for the second node when the first clock signal is at the second level;
• the reset control circuit is connected to the first clock signal terminal, the second clock signal terminal, the first level voltage line, a second level voltage line, the first node and a third node, and configured to provide the first level from the first level voltage line for the third node when the second clock signal and the first node are both at the second level, and provide a second level from the second level voltage line for the third node when the first clock signal is at the second level;
• and
• the output circuit is connected to the first level voltage line, the second level voltage line, the second node, the third node and the output terminal, and configured to provide the second level from the second level voltage line for the output terminal when the second node is at the second level, and provide the first level from the first level voltage line for the output terminal when the third node is at the second level.