Shift register unit, gate driving circuit and driving method thereof

A gate driving circuit, comprising N stages of a shift register unit, wherein the shift register unit comprises:

• an input sub-circuit connected between a signal input terminal and a pull-up node, and configured to input a signal to the pull-up node,
• an output sub-circuit connected between the pull-up node and a signal output terminal, and configured to output a pulse signal to the signal output terminal under control of the pull-up node;
• a reset sub-circuit connected between a reset terminal, the pull-up node, and the signal output terminal, and configured to reset the pull-up node and the signal output terminal under control of the reset terminal;
• and
• a clock signal selection sub-circuit having input terminals connected to a first clock signal terminal and a second clock signal terminal, control terminals connected to a first control terminal and a second control terminal, and a first output terminal connected to the output sub-circuit, and configured to select to provide either a first clock signal or a second clock signal to the output sub-circuit according to voltage levels at the first control terminal and the second control terminal, as an input clock signal to the output sub-circuit,
• wherein the input clock signal is the same as one of the first clock signal and the second clock signal in a case where the voltage levels at the first control terminal and the second control terminal are opposite,
• wherein a shift register unit in a k-th stage is configured to scan a corresponding gate line, and a signal output terminal of the shift register unit in the k-th stage is connected to a signal input terminal of the shift register unit in an (k+1)-th stage via a first switching transistor corresponding to the k-th stage and further connected to a signal input terminal of the shift register unit in a (k+2)-th stage via a second switching transistor corresponding to the k-th stage, where k≥3, N and k are integers, and
• a signal input terminal of the shift register unit in the k-th stage is connected to a signal output terminal of the shift register unit in a (k−1)-th stage via a third switching transistor corresponding to the k-th stage and further connected to an output terminal of the shift register unit in a (k−2)-th stage via a fourth switching transistor corresponding to the k-th stage.