Shift register, circuit and driving method thereof, gate drive circuit and display device

A shift register circuit comprising:

• an initialization circuit configured to set a first node at an inactive potential in response to an initialization pulse from an initialization terminal being active;
• a first node control circuit configured to set the first node at an active potential in response to an input pulse from an input terminal being active and to set the first node at the inactive potential in response to at least one of a reset pulse from a reset terminal being active or a second node being at the active potential, the input pulse being immediately subsequent to the initialization pulse;
• a second node control circuit configured to set the second node at the inactive potential in response to the first node being at the active potential and to set the second node at the active potential in response to the first node being at the inactive potential and a first clock signal from a first clock terminal being active;
• and
• an output circuit configured to set an output terminal at the active potential in response to the first node being at the active potential and a second clock signal from a second clock terminal being active and to set the output terminal at the inactive potential in response to the second node being at the active potential;
• wherein the initialization circuit is further configured to set the first node at the inactive potential by way of the first node control circuit by setting the second node at the active potential.