Pixel circuit, driving method thereof and display device

A pixel circuit, comprising:

• a light emitting unit;
• a drive transistor comprising a first electrode being connected to a first terminal of the light emitting unit, and configured to drive the light emitting unit to emit light so as to display an image frame;
• and
• a control circuit connected with a gate of the drive transistor and the first electrode of the drive transistor and configured to control the drive transistor according to signals of control lines, the controlling comprising:
• resetting, in a reset stage of the image frame, a voltage of the first electrode of the drive transistor by applying a reset voltage, and sensing, in a sense stage, a threshold voltage of the drive transistor by applying a reference voltage,
• the control circuit being further configured to control, in an offset elimination stage arranged at the beginning of the image frame and prior to the reset stage, the drive transistor to be switched off, which drive transistor was in an ON state at the end of a previous image frame;
• wherein the drive transistor comprises a second electrode being connected to a first voltage terminal, a second terminal of the light emitting unit is connected to a second voltage terminal, and the control lines comprises a first gate line, a second gate line, a data line and a sense line, the control circuit further comprising;
• a first transistor, comprising a gate being connected to the first gate line, a first electrode being connected to the data line, and a second electrode being connected to the gate of the drive transistor, and the first transistor being configured to be switched off under control of the first gate line in the offset elimination stage;
• and
• a second transistor, comprising a gate being connected to the second gate line, a first electrode being connected to the first electrode of the drive transistor, a second electrode being connected to the sense line, and the second transistor being configured to be switched on under control of the second gate line in the offset elimination stage such that the first electrode of the drive transistor conductively connects with the sense line and the voltage of the first electrode of the drive transistor is elevated by charging a parasitic capacitor of the sense line;
• wherein the drive transistor is configured to be switched off in the offset elimination stage when the voltage of the first electrode of the drive transistor is elevated to a level that makes a gate-source voltage of the drive transistor smaller than a threshold voltage.