Gate driving circuit, shift register and driving control method thereof

A shift register, comprising:

• a gate signal generation circuit configured to generate a first gate signal for gating transistors, wherein the gating transistors comprise a first gating transistor and a second gating transistor coupled in series;
• a gate signal output control circuit electrically coupled to the gate signal generation circuit and the gating transistors, and configured to receive a first level signal and output the first gate signal to the first gating transistor and the second gating transistor under control of the first level signal;
• and
• a control circuit configured to receive a second level signal, a first control signal, and a second control signal, and configured to output the first control signal to the first gating transistor and output the second control signal to the second gating transistor under control of the second level signal;
• wherein the gate signal generation circuit comprises:
• an input sub-circuit configured to receive an input signal and a reset signal, control a potential at a pull-up node under control of the input signal, and pull down the potential at the pull-up node under control of the reset signal;
• an output sub-circuit configured to receive a clock signal, and output the clock signal as the first gate signal under control of the potential at the pull-up node;
• a first pull-up sub-circuit configured to receive a third control signal, and control as potential at a pull-down node under control of the third control signal;
• a first pull-down sub-circuit configured to pull-down the potential at the pull-down node under control of the potential at the pull-up node, and pull down the potential at the pull-up node under control of the potential at the pull-down node;
• and
• a second pull-down sub-circuit electrically coupled to the gating transistors and the pull-down node, and configured to pull down a voltage output to the gate of the first gating transistor and the gate of the second gating transistor under control of the potential at the pull-down node.