Shift register unit and method for driving the same, gate driving circuit and display apparatus

A shift register unit, comprising an input signal terminal configured to receive an input signal, a clock signal terminal configured to receive a clock signal, a first voltage terminal configured to receive a first constant voltage, a second voltage terminal configured to receive a second voltage signal, a third voltage terminal configured to receive a third voltage signal, an output signal terminal configured to output a gate control signal, and a reset signal terminal configured to receive a reset signal, the shift register unit further comprising:

• an input sub-circuit connected to the input signal terminal and a pull-up control node, and configured to charge the pull-up control node under control of the input signal;
• an output sub-circuit connected to the pull-up control node, the clock signal terminal, the first voltage terminal, and the output signal terminal, and configured to output the first constant voltage to the output signal terminal under control of the clock signal and the pull-up control node;
• and
• a reset sub-circuit connected to the pull-up control node, the reset signal terminal, and the third voltage terminal respectively, and configured to reset the pull-up control node to the third voltage under control of the reset signal,
• wherein the output sub-circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor, wherein:
• the first transistor has a gate connected to the clock signal terminal, a first electrode connected to the pull-up control node, and a second electrode connected to a gate of the second transistor via a first node;
• the second transistor has a first electrode connected to the first voltage terminal, and a second electrode connected to the output signal terminal;
• the first capacitor has a first terminal connected to the output signal terminal, and a second terminal connected to the first node;
• the second capacitor has a first terminal connected to the pull-up control node, and a second terminal connected to the first terminal of the first capacitor;
• the third transistor has a gate connected to the input signal terminal, a first electrode connected to the second voltage terminal, and a second electrode connected to the first node;
• the fourth transistor has a gate connected to the reset signal terminal, a first electrode connected to the second voltage terminal, and a second electrode connected to the first node;
• and
• the fifth transistor has a gate connected to a pull-down control node, a first electrode connected to the second voltage terminal, and a second electrode connected to the output signal terminal.