Graphics surface addressing

A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:

• graphics processing circuitry configured to access a graphics surface based on an address in a surface space assigned to the graphics surface;
• first translation circuitry configured to:
• access one or more entries in a set of multiple translation entries for pages of the surface space, wherein the translation entries are stored using addresses in a virtual space and map pages of the surface space to the virtual space;
• and
• translate address information for the surface space to address information in the virtual space based on one or more of the translation entries;
• wherein the translation entries are configurable by a graphics program executed by the circuit, wherein the graphics program initially maps only a portion of the surface space to the virtual space;
• and
• wherein the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry;
• and
• second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface.

A method, comprising:

• accessing, by graphics processing circuitry, a graphics surface based on an address in a surface space assigned to the graphics surface;
• configuring, by the graphics processing circuitry based on execution of a graphics program, a set of multiple translation entries, wherein the graphics program is configured to initially map only a portion of the surface space to a virtual space;
• accessing, by first translation circuitry, one or more entries in the set of multiple translation entries for pages of the surface space, wherein the translation entries are stored using addresses in the virtual space and map pages of the surface space to the virtual space;
• translating, by the first translation circuitry, address information for the surface space to address information in the virtual space based on one or more of the translation entries;
• providing, by the graphics processing circuitry, an address for the access to the graphics surface based on translation by the first translation circuitry;
• and
• translating, by second translation circuitry, the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface.