On-chip communication system for neural network processors
AssigneeAlibaba Group Holding Limited
InventorJian Chen
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Abstract
The present disclosure provides an on-chip communication system for neural network processors, a processing device, and a method for operating on an on-chip communication system. The system can include a cluster manager configured to generate a global signal, and a plurality of tile units in a tile array coupled with the cluster manager, each including two connectors and a node connected between the two connectors.
Claims18
An on-chip communication system for artificial neural network processors, comprising:
- a cluster manager configured to:
- receive a task,
- determine available tile units of a tile array for the task,
- generate the global signal according to available tile units of the tile array, and
- connect the available tile units into a ring topology based on the global signal;
- a bus;
- a plurality of tile units in the tile array, the plurality of tile units are communicatively coupled with the cluster manager via the bus, wherein each tile unit includes a first set of connectors and at least one node that is connected between at least two connectors of the first set of connectors, wherein the at least one node is configured to acquire the global signal;
- and
- a control unit configured to:
- generate at least one of a transmission enable signal, a receiving enable signal, and a mode signal based on the global signal acquired via the bus, and
- generate a selection signal that is based on the global signal, wherein the selection signal configures one or more connectors of the first set of connectors.
A processing device communicatively coupled to one of a first set of connectors via a first terminal and to another one of the first set of connectors via a second terminal, comprising:
- a bypass bus connected between the first and second terminals and configured to communicate data signals between the first and second terminals;
- a buffer bus connected between the first and second terminals and configured to buffer the data signals;
- and
- one or more multiplexers configured to enable one of the bypass bus and the buffer bus according to a mode signal, wherein each connector of the first set of connectors comprises:
- a first gate communicatively coupled to the processing device and a connector of a second set of connectors, wherein the first gate is configured to be enabled when a selection signal is asserted;
- a second gate communicatively coupled to the processing device and a connector of a third set of connectors, wherein the second gate is configured to be enabled when the selection signal is asserted;
- and
- a third gate communicatively coupled to the connector of the second set of connectors and the connect of the third set of connectors, wherein the third gate is configured to be enabled when the selection signal is disasserted, wherein the selection signal is generated by a control unit based on a global signal.
Dependencies are inferred from the claim text.