Neural network processor with direct memory access and hardware acceleration circuits

A method of executing a dynamically adaptive neural network, the method comprising:

• creating and storing, by a central processing unit (CPU), a multi-level linked list and instructions determined based on the multi-level linked list in contiguous blocks of memory, the instructions representing a neural network, the multi-level linked list including a first linked list representing a topology of the neural network and interconnections between neurons thereof, a second linked list indicating a memory location of the memory from which to begin transferring data to hardware acceleration (HA) circuitry in forward propagation of the neural network, and a third linked list including a starting memory address for each layer of the neural network in reverse order;
• transferring, by direct memory access (DMA) circuitry, the instructions from the contiguous blocks of the memory to hardware acceleration (HA) circuitry;
• executing, by the HA circuitry, the neural network the instructions to implement the neural network;
• dynamically modifying the multi-level linked list during execution of the neural network by the HA circuitry to perform machine learning;
• and
• generating the instructions in the contiguous blocks of the memory, by the CPU, based on the multi-level linked list.

At least one non-transitory machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the following operations:

• creating and storing, by a central processing unit (CPU), a multi-level linked list and instructions determined based on the multi-level linked list in contiguous blocks of memory, the instructions representing a neural network, the multi-level linked list including a first linked list representing a topology of the neural network and interconnections between neurons thereof, a second linked list indicating a memory location of the memory from which to begin transferring data to hardware acceleration (HA) circuitry in forward propagation of the neural network, and a third linked list including a starting memory address for each layer of the neural network in reverse order;
• transferring, by direct memory access (DMA) circuitry, the instructions in the contiguous blocks of the memory to hardware acceleration (HA) circuitry;
• executing, by the HA circuitry, the instructions to implement the neural network;
• dynamically modifying the multi-level linked list, by the CPU, during execution of the neural network by the HA circuitry to perform machine learning;
• and
• generating the instructions in the contiguous blocks of the memory, by the CPU, based on the multi-level linked list.