Method and system for latch-up prevention

An integrated circuit design system, comprising:

• a processor;
• computer readable media accessible by the processor, the computer readable media storing a cell library defining a plurality of functional cells configured to perform a predefined function and a plurality of tap cells including modeled AC and DC current information for each of the functional cells, the computer readable media storing instructions that when executed by the processor implement a method, comprising:
• receiving an integrated circuit design;
• selecting a plurality of the functional cells from the cell library based on the integrated circuit design;
• arranging the plurality of the functional cells into a floor plan;
• arranging a plurality of the tap cells into predetermined locations of the floor plan;
• determining potential latchup locations in the floor plan based on the AC and DC current information for each of the functional cells in the floor plan stored in the computer readable media.

A method of designing an integrated circuit, comprising:

• receiving an integrated circuit design;
• determining a floor plan for the integrated circuit design, wherein the floor plan includes an arrangement of a plurality of functional cells configured to perform a predefined function and a plurality of tap cells, the floor plan including an outer periphery having a first border and a second border opposite the first border, and the floor plan includes a plurality of rows in which the plurality of functional cells and tap cells are arranged, the plurality of rows including a first row directly adjacent the first border and a second row directly adjacent the second border;
• and
• placing only tap cells in the first row and the second row;
• wherein at least one step of the method is performed by a processor.