Tool to create a reconfigurable interconnect framework

A method, comprising:

• accessing, using processing circuitry, a configuration template of a reconfigurable interconnect framework;
• editing, using the processing circuitry, parameters of the configuration template, the editing including:
• setting a first number of output ports of a reconfigurable stream switch, each output port having an output port architectural composition, wherein the output port architectural composition is defined by a plurality of N data paths, the plurality of N data paths including A data outputs and B control outputs, wherein N, A, and B are non-zero integers;
• and
• setting a second number of input ports of the reconfigurable stream switch, each input port having an input port architectural composition, wherein the input port architectural composition is defined by a plurality of M data paths, the plurality of M data paths including A data inputs and B control inputs;
• and
• functionally combining, using the processing circuitry, the configuration template with a plurality of modules from a logic block (IP) library to produce a register transfer level (RTL) circuit model including a model of a reconfigurable interconnect framework.

A non-transitory computer-readable medium storing computer-executable instructions, which when executed by one or more processing devices cause the one or more processing devices to perform a method, the method comprising:

• accessing a configuration template of a reconfigurable interconnect framework;
• editing parameters of the configuration template, the editing including:
• setting a first number of output ports of a reconfigurable stream switch, each output port having an output port architectural composition, wherein the output port architectural composition is defined by a plurality of N data paths, the plurality of N data paths including A data outputs and B control outputs, wherein N, A, and B are non-zero integers;
• and
• setting a second number of input ports of the reconfigurable stream switch, each input port having an input port architectural composition, wherein the input port architectural composition is defined by a plurality of M data paths, the plurality of M data paths including A data inputs and B control inputs;
• and
• functionally combining, using the processing circuitry, the configuration template with a plurality of modules from a logic block (IP) library to produce a register transfer level (RTL) circuit model including a model of a reconfigurable interconnect framework.