Systems and methods for estimating wire capacitance in a register-transfer level circuit design

A system for estimating capacitance of a net in a register-transfer level (RTL) circuit design, comprising:

• one or more non-transitory storage medium storing a reference post-layout design for the RTL circuit design;
• RTL power estimation software stored on the one or more non-transitory storage medium and executable by one or more processors, the RTL power estimation software when executed being configured to,
• determine an average fanout length for each respective gate-level net within the reference post-layout design, wherein the average fanout length is determined based on coordinate information identifying source and sink pins for the respective gate-level nets within the reference post-layout design;
• determine an overall average fanout length and a standard deviation for the gate-level nets within the reference post-layout design
• classify a gate-level net within the reference post-layout design based on a difference between an average fanout length for the gate-level net and the overall average fanout length with the standard deviation,
• generate a parasitic model for the gate-level net, the parasitic model identifying a total wire capacitance;
• store the parasitic model in a database according to the classification of the gate-level net,
• classify a net from the RTL circuit design based on a number of modules crossed by one or more fanouts within the net from the RTL circuit design, and
• select the parasitic model in the database to estimate capacitance for the net from the RTL circuit design, wherein the parasitic model in the database is selected based on the classification of the gate-level net and the classification of the net form the RTL circuit design.

A non-transitory computer-readable storage medium comprising instructions for which when executed cause a processing system to execute steps comprising:

• determining, by the processor, an average fanout length for each respective gate-level net within a reference post-layout design for the RTL circuit design, wherein the average fanout length is determined based on coordinate information identifying source and sink pins for the respective gate-level nets within the reference post-layout design;
• determining, by the processor, an overall average fanout length and a standard deviation for the gate-level nets within the reference post-layout design
• classifying, by the processor, a gate-level net within the reference post-layout design based on a difference between an average fanout length for the gate-level net and the overall average fanout length with the standard deviation;
• generating, by the processor, a parasitic model for the gate-level net, the parasitic model identifying a total wire capacitance;
• storing the parasitic model in a database according to the classification of the gate-level net;
• classifying, by the processor, a net from the RTL circuit design based on a number of modules crossed by one or more fanouts within the net from the RTL circuit design;
• and
• selecting the parasitic model in the database to estimate capacitance for the net from the RTL circuit design, wherein the parasitic model in the database is selected based on the classification of the gate-level net and the classification of the net from the RTL circuit design.