Secure low-latency chip-to-chip communication
AssigneeMarvell Asia Pte Ltd
InventorsGeorgios Angelopoulos, Steven C. Barner, Richard E. Kessler
Life of this patent
Estimating the term…
Abstract
An encryption interface provides secure, low-latency communications between processors. A first processor block transforms initial data into encrypted data using a cipher for receipt by a second processor block, which transforms the encrypted data into decrypted data. The first processor block utilized a crypto circuit having a plurality of stages, each of which generate a subset of a cipher digit stream for encrypting the data. The second processor block receives and decrypts the encrypted data using a respective decryption circuit.
Claims20
A circuit, comprising:
- a first processor block configured to transform initial data into encrypted data using a cipher, the first processor block including:
- a first registry configured to store a first key and a first set of parameters;
- a first crypto circuit configured to generate a cipher digit stream from the first key and the first set of parameters, the first crypto circuit including a plurality of stages, each stage generating a subset of the cipher digit stream at a distinct clock cycle;
- and
- an encryption circuit configured to generate the encrypted data by applying the cipher digit stream to the initial data;
- a second processor block configured to transform the encrypted data into decrypted data, the decrypted data corresponding to the initial data, the second processor block including:
- a second registry configured to store a second key and a second set of parameters;
- a second crypto circuit configured to generate the cipher digit stream from the second key and the second set of parameters;
- a decryption circuit configured to generate the decrypted data by applying the cipher digit stream to the encrypted data;
- and
- a bus connecting the first processor block and the second processor block, the first processor block being configured to forward the encrypted data to the second processor block via the bus.
A method for high-speed low-latency secure chip-to-chip communication comprising:
- storing, by a first processor block in a first registry a first key and a first set of parameters;
- storing, by a second processor block in a second registry a second key and a second set of parameters;
- generating, by a first crypto circuit of the first processor block, a cipher digit stream from the first key and the first set of parameters, the generating consisting of a plurality of stages, each stage generating a subset of the cipher digit stream, at a distinct clock cycle;
- generating, by a second crypto circuit of the second processor block, the cipher digit stream from the second key and second set of parameters;
- generating, by an encryption circuit of the first processor block, encrypted data by applying the cipher digit stream to initial data;
- transferring, across a bus, the encrypted data from the first processor block to the second processor block;
- and
- generating, by a decryption circuit of the second processor block, decrypted data by applying the cipher digit stream to the encrypted data, the decrypted data corresponding to the initial data.
Dependencies are inferred from the claim text.