High performance QR decomposition systems and methods
AssigneeIntel Corporation
InventorMartin Langhammer
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Abstract
Based on a Modified Gram-Schmidt (MGS) algorithm, QR decomposition techniques are optimized for parallel structures that provide arithmetic-logic unit (ALU) to ALU connectivity. The techniques utilize a different loop organization, but the dependent functional sequences of the algorithm are unchanged, thereby reducing likelihood of affecting error analysis and/or numerical stability. Some integrated circuit devices (e.g., FPGA) may implement hard floating-point (HFP) circuitry, such as a digital signal processing (DSP) block, distributed memories, and/or flexible internal connectivity, which can support the discussed high performance matrix arithmetic.
Claims20
An integrated circuit device, comprising:
- a memory device communicatively coupled to circuitry, wherein:
- the memory device stores an input matrix, having dimensions of size-n;
- the circuitry comprises:
- a multiply-add datapath communicatively coupled to an output of the memory device;
- a dot product datapath communicatively coupled to an output of the multiply-add datapath, via a feed-forward coupling;
- and
- one or more elementary function blocks communicatively coupled to an output of the dot product datapath;
- and
- the circuitry comprises a hardware arrangement that utilizes both the multiply-add datapath and the dot product datapath at the same time to process the input matrix.
A tangible, non-transitory, machine-readable medium, comprising machine-readable instructions that, when executed by one or more processors, cause the processors to:
- generate one or more compute cores of a programmable integrated circuit, wherein the one or more compute cores are coupled to a memory device which stores an input matrix, having dimensions of size-n, wherein the one or more compute cores utilize a multiply-add datapath communicatively coupled to an output of the memory device, a dot product datapath communicatively coupled to an output of the multiply-add datapath, and one or more elementary function blocks communicatively coupled to an output of the dot product datapath in order to perform a QR decomposition of the input matrix to obtain computational results, wherein the multiply-add datapath and the dot product datapath are used at the same time to perform the QR decomposition of the input matrix;
- and
- provide the one or more compute cores for implementation on the programmable integrated circuit.
A hardware implemented method, comprising:
- storing an input matrix in a memory device;
- communicatively coupling a multiply-add datapath to an output of the memory device;
- communicatively coupling a dot product datapath to an output of the multiply-add data path;
- communicatively coupling one or more elementary function blocks to an output of the dot product datapath;
- and
- performing a QR decomposition of the input matrix to obtain computational results, using the multiply-add datapath, the dot product datapath, and the one or more elementary function blocks, wherein the multiply-add datapath and the dot product datapath are used at the same time to perform the QR decomposition of the input matrix.
Dependencies are inferred from the claim text.