Partitioning in a compiler flow for a heterogeneous multi-core architecture

A computer system, comprising:

• a memory configured to store program code;
• and
• a processor configured to execute the program code to place kernels of an application in a data processing engine array (DPE) of a system on chip (SOC) by:
• obtaining a graph of the application having nodes representing the kernels and edges representing communication between the kernels;
• sorting the kernels based on runtime ratio associated with each of the kernels;
• processing the sorted kernels sequentially to place into partitions;
• determining an execution order of kernels in each of the partitions;
• and
• generating implementation data for the SOC for implementing the application therein based on the determined partitions and execution order for each of the partitions.