Triple-data-rate technique for a synchronous link

An apparatus, comprising:

• a plurality of receivers, each receiver being coupled to a wire of a serial bus;
• a clock generator configured to provide sampling edges in a receive clock signal, wherein the sampling edges correspond to edges of pulses in a clock signal received from a first wire of the serial bus, wherein each pulse includes a rising edge and a falling edge;
• a decoder configured to capture first data from a double data rate (DDR) encoded data signal received from a transmitting device over a second wire of the serial bus using the sampling edges;
• and
• a pulse-width demodulator configured to extract at least one bit of second data from encoded by the transmitting device in each pulse in the clock signal, wherein the second data is encoded by the transmitting device in durations of the pulses in the clock signal.

A method performed at a transmitting device coupled to a multi-wire serial bus, comprising:

• providing first data in a data signal to be transmitted on a first wire of the multi-wire serial bus;
• providing a series of pulses in a clock signal to be transmitted on a second wire of the multi-wire serial bus, wherein the first data is transmitted in accordance with double data rate (DDR) timing by transmitting bits of the first data on both rising edges and falling edges of the clock signal;
• encoding second data in the clock signal by controlling a duration of each pulse in the series of pulses based on a value of one or more bits of the second data;
• and
• transmitting the data signal and the clock signal over the multi-wire serial bus.

An apparatus, comprising:

• a plurality of line drivers, each line driver being coupled to a wire of a serial bus;
• an encoder configured to encode first data in a data signal to be transmitted through a first line driver;
• a clock generator configured to provide a series of pulses in a clock signal to be transmitted through a second line driver, wherein the first data is transmitted in accordance with double data rate (DDR) timing by transmitting bits of the first data on both rising edges and falling edges of the clock signal;
• and
• a pulse-width modulator configured to encode second data in the clock signal by controlling a duration of each pulse in the series of pulses based on a value of one or more bits of the second data.