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US 10,872,047 B2Granted
Method and apparatus for processor standby
AssigneeAdvanced Micro Devices, Inc.
InventorGreg Sadowski
Life of this patent
Estimating the term…
Abstract
A method of and device for removing a processor from a low power mode. The method includes and the device provides for performing multiple processor start-up tasks in parallel. Memory interface training between the processor and memory and restoration and initialization of the processor are performed in parallel with each other and with a serial bus controller entering serial bus training to facilitate communication between the processor and a system controller.
Claims18
A method of holding a processor in a low power mode including:
- storing context data in local memory controlled by and dedicated to the processor, context data indicating a desired state of the processor upon exiting the low power mode;
- storing pointers to the context data in a system controller memory;
- and
- maintaining a portion of the local volatile memory identified by the pointers while the processor is in the lower power mode.
1 more element
A method of placing a processor in a low power mode including:
- storing processor state information in volatile memory controlled by and dedicated to the processor;
- storing pointers to locations within the volatile memory where the state information is stored;
- placing the volatile memory into a self-refresh mode;
- engaging an external controller to facilitate the self-refresh mode of the volatile memory;
- and
- placing the processor into a low power mode such that the processor is unable to facilitate the self-refresh mode.
3 more elements
A computing device including:
- a processor;
- a system controller;
- a first volatile memory dedicated to the processor, the first volatile memory storing first information regarding a desired state for the processor;
- a second memory storing data pointers to the first information, the second memory being accessible to the system controller;
- and
- a controller operable to manage the refreshing of the first volatile memory while the processor is in a low power mode.
3 more elements
Dependencies are inferred from the claim text.