Testing hardware in a quantum computing system

A quantum computing system, comprising:

• a quantum processor cell comprising a plurality of qubit devices;
• classical control hardware comprising controllers and signal hardware coupled to the quantum processor cell for operating components in the quantum processor cell;
• and
• a classical computer system coupled to the classical control hardware and configured to perform operations, comprising;
• receiving a user-submitted quantum computing program submitted from an access node;
• running the user-submitted quantum computing program in the quantum computing system;
• running a hardware test program in the quantum computing system, wherein running the hardware test program comprises:
• defining a test domain in the quantum computing system, the test domain comprising a set of qubits in the quantum processor cell and corresponding components of the classical control hardware;
• defining a target distribution over measured bit patterns for the test domain;
• producing a control sequence, configured to generate the target distribution;
• executing the control sequence to produce output bit patterns in the test domain of the quantum computing system;
• recording the output bit patterns;
• repeating the executing and recording;
• calculating correlations between the output bit patterns to generate at least one figure of merit;
• and
• evaluating the at least one figure of merit to determine a likelihood of a presence of one or more faults;
• and
• sending, to the access node, output data based on running the user-submitted quantum computing program and the hardware test program.