Method to deliver in-DRAM ECC information through DDR bus

A memory controller, comprising:

• read circuitry to request an original data at an address stored in at least two data chips;
• parity circuitry to calculate a parity from the original data received from the at least two data chips;
• pollution pattern analysis circuitry to compare the parity with at least two pollution patterns programmed into the at least two data chips to identify a data chip with an error, wherein the original data returned from the identified data chip with the error is polluted using one of the at least two pollution patterns;
• and
• error correction circuitry to correct the error in the original data received from the identified data chip with the error.