Non volatile memory controller device and method for adjustment

A method of providing one or more adjusted log likelihood ratio (LLR) values of a plurality of bits in a codeword to a low-density parity check (LDPC) decoder, the plurality of bits representing a plurality of charge states of a plurality of memory cells of a non-volatile memory, the method comprising:

• storing in a non-volatile memory controller communicatively coupled to the non-volatile memory one or more LLR values associated with the plurality of bits;
• determining, by translation circuitry, a plurality of levels of the plurality of charge states represented by the plurality of bits;
• generating, by a distribution processor,
• a first distribution of a population of the plurality of levels at a first time, and
• a second distribution of the population of the plurality of levels at a second time after the first time;
• generating, by an LLR generator, the one or more adjusted LLR values of the plurality of bits based on a comparison between the first and second distributions;
• and
• decoding, by the LDPC decoder, the codeword according to the one or more adjusted LLR values.