Internal error checking and correction (ECC) with extra system bits

A system comprising:

• a data bus of signal lines;
• a memory controller coupled to the data bus;
• and
• M dynamic random access memory (DRAM) devices coupled to the memory controller in parallel via the data bus, where M is an integer greater than 1, the DRAM devices including:
• a memory array with addressable memory locations;
• an internal error checking and correction (ECC) circuit to perform internal ECC, including to generate and apply check bits within the DRAM device, wherein the memory array is to provide 2N memory locations for N+1 internal check bits for internal ECC of 2{circumflex over ( )}N data bits, where N is an integer greater than 1;
• and
• a hardware input/output interface coupled to the memory controller via the data bus, wherein the input/output interface is to provide access to the memory controller to one or more of the 2N memory locations not used by the N+1 internal check bits as extra bits for system ECC information, wherein the system ECC information is separate from the internal ECC;
• wherein the M DRAM devices are to exchange the 2{circumflex over ( )}N data bits and bits for the one or more 2N memory locations not used by the N+1 internal check bits over a 2N transfer cycle burst.