US 10,872,009 B2 · Mitigating a voltage condition of a memory cell in a memory sub-system

Abstract

A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

Claims16

Dependent claims

A system comprising:

a memory component;
and
a processing device, operatively coupled with the memory component, to:
determine whether a particular memory cell of the memory component has transitioned from a state associated with a first error rate to another state associated with a second error rate based on a number of first operations that have been performed on one or more memory cells that are proximate to the particular memory cell, the second error rate corresponding to a higher number of errors than the first error rate;
and
in response to determining that the particular memory cell has transitioned from the state associated with the first error rate to the another state associated with the second error rate, perform a second operation on the particular memory cell to transition the particular memory cell from the another state associated with the second error rate to the state associated with the first error rate.

3 more elements

A method comprising:

determining whether a particular memory cell of a memory component has transitioned from a state associated with a first error rate to another state associated with a second error rate based on a number of first operations that have been performed on one or more memory cells that are proximate to the particular memory cell, the second error rate corresponding to a higher number of errors than the first error rate;
and
in response to determining that the particular memory cell has transitioned from the state associated with the first error rate to the another state associated with the second error rate, performing, by a processing device, a second operation on the particular memory cell to transition the particular memory cell from the another state associated with the second error rate to the state associated with the first error rate.

Dependencies are inferred from the claim text.

Facts

Application

16/045,641Filed 25 Jul 2018 · us provisional application

Priority

8 Feb 2018

Published

US 2019/0243704 A18 Aug 2019

Granted

22 Dec 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification28 codes

G11C 16/34
Auxiliary circuits, e.g. for writing into memory: determination of programming status, e.g. threshold voltage, overprogramming or…
G06F 3/0619
Improving the reliability of storage systems: in relation to data integrity, e.g. data losses, bit errors
G06F 3/0634
Configuration or reconfiguration of storage systems: by changing the state or mode of one or more devices
G06F 3/0679
Single storage device: non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Mitigating a voltage condition of a memory cell in a memory sub-system

Life of this patent

Mitigating a voltage condition of a memory cell in a memory sub-system

Life of this patent

Abstract

Claims16