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US 10,872,004 B2Granted
Workload scheduling and coherency through data assignments
AssigneeIntel Corporation
InventorsPiotr Rozen, Sagar Koorapati
Life of this patent
Estimating the term…
Abstract
Systems, apparatuses and methods may provide for technology that assigns a plurality of data portions associated with a workload to a plurality of cores, wherein each data portion from the plurality of data portions is only modifiable by a respective one of the plurality of cores. The technology may further pass a message between the plurality of cores to modify one or more of the data portions in response to an identification that the one or more of the data portions are unmodifiable by one or more of the plurality of cores.
Claims17
A computing device comprising:
- a host processor including a plurality of cores, wherein the plurality of cores includes a first core and a second core;
- and a memory coupled to the host processor, the memory including executable program instructions, which when executed by the host processor, cause the host processor to:
- assign a plurality of data portions associated with a workload to the plurality of cores, wherein each data portion of the plurality of data portions is only modifiable by a respective one of the plurality of cores, wherein a first data portion from the plurality of data portions is only modifiable by the first core;
- identify, with the first and second cores, a queue that is to be only accessible by the first and second cores from the plurality of the cores and is dedicated to communication between the first and second cores;
- identify, with the second core, that the second core is to process an operation that is to modify the first data portion;
- write, with the second core, an instruction into the queue to instruct the first core to execute at least part of the operation to modify the first data portion in response to a determination that the second core is unable to modify the first data portion;
- read, with the first core, the instruction from the queue to cause the first core to execute the at least the part of the operation and modify the first data portion;
- and
- pass a message between the plurality of cores to modify one or more of the data portions in response to an identification that the one or more of the data portions are unmodifiable by one or more of the plurality of cores.
6 more elements
A semiconductor apparatus comprising:
- one or more substrates;
- and a
- control logic coupled to the one or more substrates, wherein the control logic is implemented in one or more of configurable logic or fixed-functionality logic hardware, the control logic coupled to the one or more substrates to:
- assign a plurality of data portions associated with a workload to a plurality of cores that is to include a first core and a second core, wherein each data portion from the plurality of data portions is only modifiable by a respective one of the plurality of cores, wherein a first data portion from the plurality of data portions is only modifiable by the first core;
- identify, with the first and second cores, a queue that is to be only accessible by the first and second cores from the plurality of the cores and is dedicated to communication between the first and second cores;
- identify, with the second core, that the second core is to process an operation that is to modify the first data portion;
- write, with the second core, an instruction into the queue to instruct the first core to execute at least part of the operation to modify the first data portion in response to a determination that the second core is unable to modify the first data portion;
- read, with the first core, the instruction from the queue to cause the first core to execute the at least the part of the operation and modify the first data portion;
- and
- pass a message between the plurality of cores to modify one or more of the data portions in response to an identification that the one or more of the data portions are unmodifiable by one or more of the plurality of cores.
7 more elements
At least one computer readable storage medium comprising a set of executable program instructions, which when executed by a computing system, cause the computing system to:
- assign a plurality of data portions associated with a workload to a plurality of cores that is to include a first core and a second core, wherein each data portion from the plurality of data portions is only modifiable by a respective one of the plurality of cores, wherein a first data portion from the plurality of data portions is only modifiable by the first core;
- identify, with the first and second cores, a queue that is to be only accessible by the first and second cores from the plurality of the cores and is dedicated to communication between the first and second cores;
- identify, with the second core, that the second core is to process an operation that is to modify the first data portion;
- write, with the second core, an instruction into the queue to instruct the first core to execute at least part of the operation to modify the first data portion in response to a determination that the second core is unable to modify the first data portion;
- read, with the first core, the instruction from the queue to cause the first core to execute the at least the part of the operation and modify the first data portion;
- and
- pass a message between the plurality of cores to modify one or more of the data portions in response to an identification that the one or more of the data portions are unmodifiable by one or more of the plurality of cores.
4 more elements
A method implemented with at least one processor having thereon memory-stored instructions which, when executed by the at least one processor, cause the at least one processor to perform the method, comprising:
- assigning a plurality of data portions associated with a workload to a plurality of cores that includes a first core and a second core, wherein each data portion from the plurality of data portions is only modifiable by a respective one of the plurality of cores, wherein a first data portion from the plurality of data portions is only modifiable by the first core;
- identifying, with the first and second cores, a queue that is to be only accessible by the first and second cores from the plurality of the cores and is dedicated to communication between the first and second cores;
- identifying, with the second core, that the second core is to process an operation that is to modify the first data portion;
- writing, with the second core, an instruction into the queue to instruct the first core to execute at least part of the operation to modify the first data portion in response to a determination that the second core is unable to modify the first data portion;
- reading, with the first core, the instruction from the queue to cause the first core to execute the at least the part of the operation and modify the first data portion;
- and
- passing a message between the plurality of cores to modify one or more of the plurality of data portions in response to an identification that the one or more of the data portions are unmodifiable by one or more of the plurality of cores.
4 more elements
Dependencies are inferred from the claim text.