Detection, modeling and application of memory bandwith patterns

A system, comprising:

• one or more computing devices;
• and
• a memory coupled to the one or more computing devices comprising program instructions executable by the one or more computing device to:
• model memory bandwidth patterns for a multi-core system comprising multiple sockets, each of which comprises multiple cores, wherein said modeling is based at least in part on results from executing one or more profiling sessions on the multi-core system and the values of the one or more machine performance counters configured to indicate amounts of data transferred on respective sockets of the multi-core system;
• wherein to model the memory bandwidth patterns, the program instructions are further executable to:
• execute a workload on the multi-core system, comprising executing multiple threads of the workload on the multi-core system;
• determine, for a plurality of bandwidth classes, respective amounts of the workload's total memory accesses, in terms of amount of data transferred, that corresponds to respective ones of the plurality of bandwidth classes, wherein the plurality of bandwidth classes represent different types of memory access by the workload when executing on the multi-core system, wherein said determining is based, at least in part, on the values of the machine performance counters;
• wherein the bandwidth classes comprise one or more of:
• static memory access representing accesses to memory allocated in a single memory bank used by all threads of the workload;
• local memory access representing accesses to memory by threads on the same sockets as which the memory is allocated;
• interleaved shared memory access representing accesses to memory allocated evenly across the sockets;
• or
• per-thread shared memory access representing accesses to memory allocated by one thread and used by all threads of the workload;
• and
• allocate, for an application executing on the multi-core system, memory to be accessed by one or more threads of the application, according to the modeled memory bandwidth patterns.

A non-transitory, computer-readable storage medium storing program instructions that when executed on one or more computer devices comprising persistent memory cause the one or more computing devices to perform:

• modeling memory bandwidth patterns for a multi-core system comprising multiple sockets, each of which comprises multiple cores, wherein said modeling is based at least in part on results from executing one or more profiling sessions on the multi-core system and the values of the one or more machine performance counters configured to indicate amounts of data transferred on respective sockets of the multi-core system;
• wherein said modeling comprises:
• executing a workload on the multi-core system, comprising executing multiple threads of the workload on the multi-core system;
• determining, for a plurality of bandwidth classes, respective amounts of the workload's total memory accesses, in terms of amount of data transferred, that corresponds to respective ones of the plurality of bandwidth classes, wherein the plurality of bandwidth classes represent different types of memory access by the workload when executing on the multi-core system, wherein said determining is based, at least in part, on the values of the machine performance counters;
• wherein the bandwidth classes comprise one or more of:
• static memory access representing accesses to memory allocated in a single memory bank used by all threads of the workload;
• local memory access representing accesses to memory by threads on the same sockets as which the memory is allocated;
• interleaved shared memory access representing accesses to memory allocated evenly across the sockets;
• or
• per-thread shared memory access representing accesses to memory allocated by one thread and used by all threads of the workload;
• and
• providing an application programming interface (API) configured to provide, at runtime, the modeled memory bandwidth patterns to applications executing on the multi-core system.