Process-based multi-key total memory encryption
AssigneeIntel Corporation
InventorsWajdi Feghali, Vinodh Gopal, Kirk Yap, Sean Gulley, Raghunandan Makaram
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AssigneeIntel Corporation
InventorsWajdi Feghali, Vinodh Gopal, Kirk Yap, Sean Gulley, Raghunandan Makaram
Estimating the term…
Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.
A method for decrypting data including:
A per-process memory encryption system, including, in each core of a multi-core processor:
A per-process memory encryption system, including, in each hardware thread of a core:
Dependencies are inferred from the claim text.