System and method to control the number of active vector lanes in a processor

An integrated circuit comprising:

• a data processor that includes:
• a plurality of execution units that include at least a first execution unit and a second execution unit;
• a register file;
• a data path including a plurality of lanes and coupling the register file to each of the first and second execution units, wherein the data path and the register file are arranged so that writing to the register file by the first execution unit and by the second execution unit is allowed over the data path, reading from the register file by the first execution unit is allowed over the data path, and reading from the register file by the second execution unit is not allowed over the data path;
• and
• a power control circuit configured to, when a transfer of data between the register file and either of the first execution unit and the second execution unit uses less than all of the lanes of the data path, power down the lanes of the data path not used for the transfer of the data.