US 10,871,964 B2 · Architecture for sparse neural network acceleration

Abstract

A method, a computer-readable medium, and an apparatus for a sparse neural network are provided. The apparatus may include a hardware accelerator. The apparatus may determine, for each pair of operands to be processed by a MAR unit, whether both operands of the pair are non-zero. The apparatus may prevent a pair of operands to be processed by the MAR unit from being loaded to a multiplier of the MAR unit when an operand of the pair of operands is zero. The apparatus may place the pair of operands into one of a plurality of queues when both operands of the pair of operands are non-zero.

Claims30

Dependent claims

A method for a deep convolutional neural network, comprising:

determining, by a load unit, for a pair of operands fetched from an operand storage to be placed into one queue of a plurality of queues for processing by a multiply-accumulate-reduce (MAR) unit, whether both operands of the pair of operands are non-zero;
and
preventing, by the load unit, the pair of operands from being placed into the plurality of queues when an operand of the pair of operands is determined to be zero.

Dependencies are inferred from the claim text.

Facts

Application

15/393,670Filed 29 Dec 2016

Published

US 2018/0189056 A15 Jul 2018

Granted

22 Dec 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 9/3001
To perform operations on data operands: arithmetic instructions
G06N 3/0464
Architecture, e.g. interconnection topology: convolutional networks [CNN, ConvNet]
G06N 3/0495
Architecture, e.g. interconnection topology: quantised networks; Sparse networks; Compressed networks
G06N 3/063
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means

Architecture for sparse neural network acceleration

Life of this patent

Architecture for sparse neural network acceleration

Life of this patent

Abstract

Claims30