Methods for using a multiplier to support multiple sub-multiplication operations

An integrated circuit, comprising:

• a multiplier circuit having a first input, a second input, and an output, wherein:
• the first input is configured to receive a first multiplicand and a second multiplicand;
• the second input is configured to receive a first multiplier and a second multiplier;
• the first multiplier is shared between the first and second multiplicands to generate at least a first product at the output of the multiplier circuit;
• the second multiplier is shared between the first and second multiplicands to generate at least a second product at the output of the multiplier circuit;
• the first multiplicand and the second multiplier are used to compute a first partial product;
• the second multiplicand and the first multiplier are used to compute a second partial product;
• a sum of the first and second partial products is generated at the output of the multiplier circuit;
• and
• the sum of the first and second partial products overflows into the second product.

An integrated circuit, comprising:

• a multiplier circuit having a first input, a second input, and an output, wherein:
• the first input is configured to receive a first multiplicand and a second multiplicand;
• the second input is configured to receive a first multiplier and a second multiplier;
• the first multiplier is shared between the first and second multiplicands to generate a first partial product;
• the second multiplier is shared between the first and second multiplicands to generate a second partial product;
• and
• the first and second partial products only partially overlap to produced bits at the output of the multiplier circuit.

An integrated circuit, comprising:

• a multiplier circuit operable to compute two floating-point mantissa multiplication operations, wherein:
• the multiplier circuit has a first input configured to receive first mantissa bits and second mantissa bits and has a second input configured to receive third mantissa bits and fourth mantissa bits;
• and
• the multiplier circuit is configured to compute a first partial product of the first and third mantissa bits, a second partial product of the first and fourth mantissa bits, a third partial product of the second the third mantissa bits, and a fourth partial product of the second and fourth mantissa bits, wherein the second partial product at least partially overlaps with the third partial product.