Block management method, memory control circuit unit and apparatus using mapping tables and block recognition machine learning with block parameters as training data

A memory storage apparatus, comprising:

• a connection interface unit, configured to electrically connect to a host system;
• a rewritable non-volatile memory module comprising a plurality of physical blocks;
• and
• a memory control circuit unit, electrically connected to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to:
• give a write command sequence for writing test data to a first physical block among the plurality of physical blocks;
• give a read command sequence for reading the test data from the first physical block among the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block;
• group the first physical block into a first block group or a second block group according to the plurality of parameters corresponding to the first physical block and a rule between the plurality of parameters and grouping of the plurality of physical blocks;
• establish a first block mapping table and a second block mapping table;
• sort physical blocks belonging to the first block group;
• map logical addresses of the first block mapping table to the physical blocks belonging to the first block group;
• sort physical blocks belonging to the second block group;
• map logical addresses of the second block mapping table to the physical blocks belonging to the second block group,
• wherein the plurality of parameters comprises a bit error position parameter that is obtained according to an error bits distribution in an upper physical programming unit, an error bits distribution in a center physical programming unit and an error bits distribution in a lower physical programming unit among test data read from each of the plurality of physical blocks, and the rule between the plurality of parameters and the grouping of the plurality of physical blocks comprises:
• grouping a physical block of the plurality of physical blocks into the first block group when test data read from the physical block is correctable in an error checking and correcting operation, and
• grouping a further physical block of the plurality of physical blocks into the second block group when further test data read from the further physical block is uncorrectable in the error checking and correcting operation and is corrected after a re-reading operation.

A memory control circuit unit, the memory control circuit unit comprising:

• a host interface, configured to electrically connect to a host system;
• a memory interface, configured to electrically connect to a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical blocks;
• and
• a memory management circuit, electrically connected to the host interface and the memory interface, wherein the memory management circuit is configured to:
• give a write command sequence for writing test data to a first physical block among the plurality of physical blocks;
• give a read command sequence for reading the test data from the first physical block among the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block;
• group the first physical block into a first block group or a second block group according the plurality of parameters corresponding to the first physical block and a rule between the plurality of parameters and grouping of the plurality of physical blocks;
• establish a first block mapping table and a second block mapping table;
• sort physical blocks belonging to the first block group;
• map logical addresses of the first block mapping table to the physical blocks belonging to the first block group;
• sort physical blocks belonging to the second block group;
• map logical addresses of the second block mapping table to the physical blocks belonging to the second block group,
• wherein the plurality of parameters comprises a bit error position parameter that is obtained according to an error bits distribution in an upper physical programming unit, an error bits distribution in a center physical programming unit and an error bits distribution in a lower physical programming unit among test data read from each of the plurality of physical blocks, and the rule between the plurality of parameters and the grouping of the plurality of physical blocks comprises:
• grouping a physical block of the plurality of physical blocks into the first block group when test data read from the physical block is correctable in an error checking and correcting operation, and
• grouping a further physical block of the plurality of physical blocks into the second block group when further test data read from the further physical block is uncorrectable in the error checking and correcting operation and is corrected after a re-reading operation.