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US 10,871,903 B2Granted
Achieving consistent read times in multi-level non-volatile memory
AssigneeIntel Corporation
InventorsAnand S. Ramalingam, Pranav Kalavade
Life of this patent
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Abstract
Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.
Claims25
A system comprising:
- a device controller apparatus including a transfer buffer;
- and
- a non-volatile memory (NVM) communicatively coupled to the device controller apparatus, the NVM including:
- a set of multi-level NVM cells that is to correspond to a lower page, one or more intermediate pages and a last page;
- and
- a chip controller apparatus that includes one or more substrates and logic, implemented in fixed-functionality hardware and coupled to the one or more substrates, the logic to:
- program the set of multi-level NVM cells,
- read from the set of multi-level NVM cells, and
- determine bit values of the lower page based on multiple comparisons between read levels to read the lower page.
6 more elements
A non-volatile memory (NVM) comprising:
- a set of multi-level NVM cells that is to correspond to a lower page, one or more intermediate pages and a last page;
- and
- a chip controller apparatus that includes one or more substrates and logic, implemented in fixed-functionality hardware and coupled to the one or more substrates, the logic to:
- program the set of multi-level NVM cells,
- read from the set of multi-level NVM cells, and
- determine bit values of the lower page based on multiple comparisons between read levels to read the lower page.
3 more elements
A method comprising:
- programming, with logic implemented in fixed-functionality hardware, a set of multi-level NVM cells, wherein the set of multi-level NVM cells correspond to a lower page, one or more intermediate pages and a last page;
- reading, with the logic, from the set of multi-level NVM cells;
- and
- determining, with the logic, bit values of the lower page based on multiple comparisons between read levels to read the lower page.
1 more element
Dependencies are inferred from the claim text.