Code generator including asynchronous counter and synchronous counter, and operating method thereof

A code generator comprising:

• an asynchronous counter configured to receive a first clock signal and to respectively output first output signals corresponding to first bits of a binary code based on the first clock signal;
• a synchronous counter configured to respectively output second output signals corresponding to second bits of the binary code based on a second clock signal obtained by dividing the first clock signal by the asynchronous counter;
• and
• a code converter configured to receive the first and second bits of the binary code and to convert the binary code into a gray code,
• wherein the code converter includes:
• a plurality of first flip-flops configured to toggle logical values of remaining logical values of the gray code other than the most significant bit (MSB) of the binary code at edges of output signals respectively corresponding to remaining bits of the first and second bits other than the MSB of the binary code, and
• a delay circuit configured to delay an output signal corresponding to the MSB of the binary code and to output the MSB of the gray code.

An operating method of a code generator, the method comprising:

• receiving a first clock signal;
• outputting a first output signal based on the first clock signal by using a first flip-flop;
• outputting second to m-th output signals by dividing a frequency of the first clock signal by using second to m-th flip-flops (m being an integer of 2 or more);
• delaying the first to m-th output signals corresponding to first to m-th bits of a code by first to m-th delay circuit, respectively;
• and
• synchronously outputting (m+1)-th to (m+n)-th output signals (n being an integer of 2 or more) corresponding to (m+1)-th to (m+n)-th bits of the code by using (m+1)-th to (m+n)-th flip-flops, at an edge of a second clock signal generated by dividing the first clock signal by using the first to m-th flip-flops.