Three-dimensional memory device and method for forming the same
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsWenyu Hua, Fandong Liu, Zhiliang Xia
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Abstract
Embodiments of a three-dimensional (3D) memory device are provided. The 3D memory device includes a substrate, a memory stack with interleaved conductive layers and dielectric layers over the substrate, an array of channel structures each extending vertically through the memory stack, and a plurality of contact hole structures each extending vertically through the memory stack and electrically connected to a common source of one or more of the channel structures. At least one of the plurality of contact hole structures is surrounded by a plurality of the channel structures of nominally equal lateral distances to the respective contact hole structure.
Claims20
A three-dimensional (3D) memory device, comprising:
- a substrate;
- a memory stack comprising interleaved conductive layers and dielectric layers over the substrate;
- an array of channel structures each extending vertically through the memory stack;
- a plurality of contact hole structures each extending vertically through the memory stack and electrically connected to a common source of one or more of the channel structures, at least one of the plurality of contact hole structures being surrounded by a plurality of the channel structures of nominally equal lateral distances to the respective contact hole structure;
- and
- a top select gate (TSG) cut extending vertically through part of the memory stack and laterally along a first lateral direction, wherein at least two contact hole structures of the plurality of contact hole structures are disposed in the TSG cut and are separated by at least two channel structures also disposed in the TSG cut.
A three-dimensional (3D) memory device, comprising:
- a substrate;
- a memory stack comprising interleaved conductive layers and dielectric layers over the substrate;
- an array of channel structures each extending vertically through the memory stack;
- an insulating structure extending vertically through the array of channel structures and laterally along a boundary of the array of channel structures;
- a plurality of contact hole structures each extending vertically through the memory stack and electrically connected to a common source of one or more of the channel structures, each of the plurality of contact hole structures being surrounded by a plurality of the channel structures;
- and
- a top select gate (TSG) cut extending vertically through part of the memory stack and laterally along a first lateral direction, wherein at least two contact hole structures of the plurality of contact hole structures are disposed in the TSG cut and are separated by at least two channel structures also disposed in the TSG cut.
Dependencies are inferred from the claim text.