Apparatuses and methods for clock leveling in semiconductor memories

An apparatus, comprising:

• a latency control circuit configured to receive a system clock and provide in first and second modes an active first control signal having a timing based on latency information and the system clock;
• a clock leveling control circuit configured to receive first and second clocks of a plurality of multiphase clocks and receive the first control signal, the clock leveling control circuit configured to provide in the first mode an active second control signal responsive to an active first control signal at a clock transition of the first clock and further configured to provide in the second mode clock leveling feedback responsive to the active first control signal at a transition of the second clock, wherein the clock leveling feedback is indicative of a timing of the data clock and system clock;
• a read clock circuit configured to receive the plurality of multiphase clocks and configured to provide the multiphase clocks responsive to the active second control signal;
• and
• a serializer circuit configured to receive data in parallel and serialize the data based on the multiphase clocks from the read clock circuit to provide the data in series.

A method, comprising:

• providing an active first control signal having a timing based on latency information and a system clock;
• receiving first and second clocks of a plurality of multiphase clocks;
• during an access operation, providing from a clock leveling control circuit an active second control signal responsive to the active first control signal at a clock transition of the first clock;
• in a clock leveling mode, providing from the clock leveling control circuit a clock leveling feedback having a logic level based on the active first control signal at a transition of the second clock;
• providing the multiphase clocks responsive to the active second control signal;
• and
• serializing parallel data based on the multiphase clocks responsive to the active second control signal to provide the data in series.