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US 10,826,506 B2Granted
Modulus divider with deterministic phase alignment
AssigneeIntegrated Device Technology, Inc.
InventorChengming He
Life of this patent
Estimating the term…
Abstract
An apparatus includes a plurality of latches and a plurality of logic gates. Each latch may be setable and resettable. The logic gates may be connected to the latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal. Each latch may be commanded into a corresponding initial state while the command signal is in an initialization state. Each latch is generally free to change states while the command signal is in a run state. A modulus division operation of the multi-modulus divider may start upon an initial edge of the input clock signal after the command signal changes from the initialization state to the run state.
Claims20
An apparatus comprising:
- a plurality of latches, each comprising a data input node, a set node, and a reset node, wherein a first number of said latches further comprise an active high enable node and a second number of said latches further comprise an active low enable node;
- and
- a plurality of logic gates connected to said latches to form a plurality of dual-modulus divider circuits making up a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal and a programming signal, wherein
- (i) each of said latches is placed in a corresponding initial state while said command signal is in an initialization state,
- (ii) each of said latches is free to change states while said command signal is in a run state,
- (iii) a modulus division operation of said multi-modulus divider starts upon an initial edge of said input clock signal after said command signal changes from said initialization state to said run state,
- (iv) a first of said dual-modulus divider circuits comprises (a) a first of said latches having said active low enable node receiving said input clock signal, said reset node receiving said command signal, and said set node set to an inactive state, (b) a second of said latches having said active high enable node receiving said input clock signal, said set node receiving said command signal, and said reset node set to said inactive state, (c) a third of said latches having said active low enable node receiving said input clock signal, said set node receiving said command signal, and said reset node set to said inactive state, and (d) a fourth of said latches having said active high enable node receiving said input clock signal, said set node receiving a logical combination of said command signal and said programming signal, and said reset node receiving a logical combination of said command signal and a complement of said programming signal, and
- (v) said output clock signal always has a correct phase alignment to said initial edge of said input clock signal.
5 more elements
An apparatus comprising:
- a first circuit configured to (i) receive a command signal, an input clock signal, a first programming signal, and a feedback signal, and (ii) generate an intermediate clock signal and an output clock signal;
- and
- a second circuit configured to (i) receive said command signal, a second programming signal, and said intermediate clock signal, and (ii) generate said feedback signal, wherein
- (a) each of a plurality of latches in both said first circuit and said second circuit comprises either an active high enable node or an active low enable node, a data input node, a set node, and a reset node,
- (b) each of said plurality of latches is placed in a corresponding initial state while said command signal is in an initialization state,
- (c) each of said plurality of latches is free to change states while said command signal is in a run state,
- (d) a modulus division operation starts upon an initial edge of said input clock signal after said command signal changes from said initialization state to said run state,
- (e) said first circuit comprises (a) a first of said latches having said active low enable node receiving said input clock signal, said reset node receiving said command signal, and said set node set to an inactive state, (b) a second of said latches having said active high enable node receiving said input clock signal, said set node receiving said command signal, and said reset node set to said inactive state, (c) a third of said latches having said active low enable node receiving said input clock signal, said set node receiving said command signal, and said reset node set to said inactive state, and (d) a fourth of said latches having said active high enable node receiving said input clock signal, said set node receiving a logical combination of said command signal and said first programming signal, and said reset node receiving a logical combination of said command signal and a complement of said first programming signal, and
- (f) said output clock signal always has a correct phase alignment to said initial edge of said input clock signal.
6 more elements
Dependencies are inferred from the claim text.