Hybrid analog-digital matrix processors
AssigneeLightmatter, Inc.
InventorsTyler J. Kenney, Martin B. Z. Forsythe, Tomo Lazovich, Darius Bunandar
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Abstract
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
Claims26
A hybrid analog-digital processor comprising:
- circuitry comprising an analog processor, wherein the circuitry is configured to perform a mathematical operation using a plurality of passes, wherein for each of the plurality of passes, the circuitry is configured to:
- determine one or more scaling factors for the pass based on a set of parameters representing a portion of a matrix;
- scale at least some parameters of the set of parameters based on the one or more scaling factors to produce a scaled set of parameters;
- program the analog processor based on the scaled set of parameters;
- generate a plurality of input analog signals based on an input data set;
- generate a plurality of output analog signals based on the plurality of input analog signals and the scaled set of parameters;
- generate a partial output data set based on the plurality of output analog signals;
- and
- scale the partial output data set based on the one or more scaling factors to produce a scaled partial output data set,
- wherein the circuitry is further configured to generate an accumulated output data set by accumulating the scaled partial output data sets generated by at least two of the plurality of passes, wherein the accumulated output data set represents a result of the mathematical operation.
A method for performing a mathematical operation using a plurality of passes through an analog processor, the method comprising:
- for each of the plurality of passes:
- determining one or more scaling factors for the pass based on a set of parameters representing a portion of a matrix;
- scaling at least some parameters of the set of parameters based on the one or more scaling factors to produce a scaled set of parameters;
- programming the analog processor based on the scaled set of parameters;
- generating a plurality of input analog signals based on an input data set;
- generating a plurality of output analog signals based on the plurality of input analog signals and the scaled set of parameters;
- generating a partial output data set based on the plurality of output analog signals;
- and
- scaling the partial output data set based on the one or more scaling factors to produce a scaled partial output data set;
- and
- generating an accumulated output data set by accumulating the scaled partial output data sets generated by at least two of the plurality of passes, wherein the accumulated output data set represents a result of the mathematical operation.
A hybrid analog-digital processor comprising:
- circuitry comprising a photonic processor, wherein the circuitry is configured to perform a mathematical operation using a plurality of passes, wherein for each of the plurality of passes, the circuitry is configured to:
- determine one or more scaling factors for the pass based on a set of parameters representing a portion of a matrix;
- scale at least some parameters of the set of parameters based on the one or more scaling factors to produce a scaled set of parameters;
- program the photonic processor based on the scaled set of parameters;
- generate a plurality of input optical signals based on an input data set;
- generate a plurality of output optical signals based on the plurality of input optical signals and the scaled set of parameters;
- generate a partial output data set based on the plurality of output optical signals;
- and
- scale the partial output data set based on the one or more scaling factors to produce a scaled partial output data set,
- wherein the circuitry is further configured to generate an accumulated output data set by accumulating the scaled partial output data sets generated by at least two of the plurality of passes, wherein the accumulated output data set represents a result of the mathematical operation.
Dependencies are inferred from the claim text.