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US 10,784,873 B1Granted
Square wave-to-sine wave converter
AssigneeTexas Instruments Incorporated
InventorsQunying Li, Shanmuganand Chellamuthu, Kemal Safak Demirci
Life of this patent
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Abstract
A circuit includes a bandpass filter and a self-tracking circuit. The bandpass filter has a first input node configured to receive an input square wave signal and an output node configured to provide an output sine wave signal. The bandpass filter includes a first binary-weighted programmable resistor array. The self-tracking circuit includes a second input node coupled to the output node. The self-tracking circuit includes a counter, and the counter includes an output node coupled to the first binary weighted programmable resistor array.
Claims15
A circuit, comprising:
- a bandpass filter having a first input configured to receive an input square wave signal and an output configured to provide an output sine wave signal, the bandpass filter comprising a first binary-weighted programmable resistor array;
- and
- a self-tracking circuit including a second input coupled to the output, the self-tracking circuit including a counter, the counter including an output coupled to the first binary weighted programmable resistor array;
- wherein:
- when a phase of the output sine wave signal leads a phase of the input square wave, the counter is configured to count up;
- and
- when the phase of the input sine wave signal lags the phase of the input square wave, the counter is configured to count down.
4 more elements
A circuit, comprising:
- a bandpass filter having a first input configured to receive an input square wave signal and an output configured to provide an output sine wave signal, the bandpass filter comprising a first binary-weighted programmable resistor array;
- and
- a self-tracking circuit including a second input coupled to the output, the self-tracking circuit including a counter, the counter including an output coupled to the first binary weighted programmable resistor array;
- wherein:
- the self-tracking circuit includes a first data flip-flop having a first clock input;
- the self-tracking circuit includes a second data flip-flop having a second clock input;
- a first time delay element having an input coupled to the first input, and having an output coupled to the first clock input;
- a second time delay element having an input coupled to the first input, and having an output coupled to the second clock input.
5 more elements
A circuit, comprising:
- a bandpass filter having a first input configured to receive an input square wave signal and an output configured to provide an output sine wave signal, the bandpass filter comprising a first programmable resistor array;
- and
- a self-tracking circuit including a comparator to compare the output sine wave signal to a reference signal to produce a comparator output signal, and the self-tracking circuit further includes a phase detector to detect whether a phase of the comparator output signal lead or lags a phase of the input square wave signal and to produce a control signal of a first state responsive to the phase of the comparator output signal leading the phase of the input square wave signal, and to produce the control signal of a second state responsive to the phase of the comparator output signal lagging the phase of the input square wave signal;
- wherein the first programmable resistor array is programmable based on the control signal.
1 more element
A circuit, comprising:
- a bandpass filter having a first input configured to receive an input square wave signal and an output configured to provide an output sine wave signal, the bandpass filter comprising a first binary-weighted programmable resistor array and a second binary-weighted programmable resistor array;
- and
- a self-tracking circuit including a second input coupled to the output, the self-tracking circuit including a phase detector and a bi-directional counter, the phase detector configured to detect a phase lead or phase lag condition, and the bi-directional counter including an output coupled to the first binary weighted programmable resistor array and to the second binary-weighted programmable resistor array.
Dependencies are inferred from the claim text.