Uplink control information transmission method, uplink control information reception method, terminal and base station

A UCI reception method, comprising:

• when a collision is present between different types of UCIs with a first TTI length and/or a collision is present between a UCI with the first TTI length and a UCI with a second TTI length,
• receiving in a second sPUCCH format the UCIs with the collision transmitted simultaneously on a predetermined sPUCCH resource corresponding to the second sPUCCH format, wherein the second sPUCCH format is a sPUCCH format with a maximum payload capacity greater than or equal to a predetermined bit value, and the predetermined sPUCCH resource corresponding to the second sPUCCH format is an additional sPUCCH resource other than a sPUCCH resource adopted by the UCIs with the collision;
• or
• determining a reception scheme for the UCIs with the collision in accordance with a sPUCCH format adopted by the UCI with the first TTI length,
• wherein the determining the reception scheme for the UCIs with the collision in accordance with the sPUCCH format adopted by the UCI with the first TTI length comprises:
• when a first sPUCCH format is adopted by the UCI with the first TTI length, receiving in the second sPUCCH format the UCIs with the collision transmitted simultaneously on the predetermined sPUCCH resource corresponding to the second sPUCCH format;
• or
• when the second sPUCCH format is adopted by the UCI with the first TTI length, receiving in the second sPUCCH format corresponding to the UCI with the first TTI length the UCIs with the collision transmitted simultaneously on the sPUCCH resource corresponding to the second sPUCCH format,
• wherein the first sPUCCH format is a sPUCCH format with a maximum payload capacity smaller than the predetermined bit value, and the second sPUCCH format is a sPUCCH format with a maximum payload capacity greater than or equal to the predetermined bit value.

A terminal, comprising a processor, a memory and a transceiver, wherein the processor is configured to read a program stored in the memory to, when a collision is present between different types of UCIs with a first TTI length and/or a collision is present between a UCI with the first TTI length and a UCI with a second TTI length,

• transmit through the transceiver the UCIs with the collision to a base station simultaneously using a second sPUCCH format on a predetermined sPUCCH resource corresponding to the second sPUCCH format, wherein the second sPUCCH format is a sPUCCH format with a maximum payload capacity greater than or equal to a predetermined bit value, and the predetermined sPUCCH resource corresponding to the second sPUCCH format is an additional sPUCCH resource other than a sPUCCH resource adopted by the UCIs with the collision;
• or
• determine a transmission scheme for the UCIs with the collision in accordance with a sPUCCH format adopted by the UCI with the first TTI length wherein the processor is further configured to read the program stored in the memory to:
• when a first sPUCCH format is adopted by the UCI with the first TTI length, transmit through the transceiver the UCIs with the collision to the base station simultaneously using a second sPUCCH format on the predetermined sPUCCH resource corresponding to the second sPUCCH format;
• or when the second sPUCCH format is adopted by the UCI with the first TTI length, transmit through the transceiver the UCIs with the collision to the base station simultaneously using a second sPUCCH format on the sPUCCH resource corresponding to the second sPUCCH format, wherein the sPUCCH resource corresponds to the UCI with the first TTI length, wherein the first sPUCCH format is a sPUCCH format with a maximum payload capacity smaller than the predetermined bit value, and the second sPUCCH format is a sPUCCH format with a maximum payload capacity greater than or equal to the predetermined bit value, wherein
• the transceiver is configured to receive and transmit data, and the memory is configured to store therein data for an operation of the processor.