Clock data recovery circuit

A clock data recovery circuit (100), comprising:

• a first detecting circuit (110), arranged to operably detect phases of a data signal (DA_IN) and a sampling clock signal (SCLK) to generate a corresponding first detection signal (DEC1);
• a first loop filter (120), coupled with the first detecting circuit (110), and arranged to operably process the first detection signal (DEC1) to generate a control signal (CTL);
• a second detecting circuit (130), arranged to operably detect phases of a reference signal (REF) and a feedback signal (FB) to generate a corresponding second detection signal (DEC2);
• a control voltage generating circuit (140), coupled with the second detecting circuit (130), and arranged to operably generate a corresponding control voltage (VC) according to the second detection signal (DEC2);
• a voltage-controlled oscillator (150), coupled with the control voltage generating circuit (140), and arranged to operably generate the sampling clock signal (SCLK) according to the control voltage (VC);
• a phase adjustment circuit (160), coupled with the first loop filter (120) and the voltage-controlled oscillator (150), and arranged to operably adjust a phase of the sampling clock signal (SCLK) according to the control signal (CTL), so as to generate a phase-adjusted signal (ACLK);
• and
• a frequency divider circuit (170), coupled with the second detecting circuit (130) and the phase adjustment circuit (160), and arranged to operably conduct a frequency division operation on the phase-adjusted signal (ACLK) to generate the feedback signal (FB).