Forward error correction mechanism for data transmission across multi-lane links

A method comprising:

• receiving, at a port, one or more outgoing symbols for transmission;
• determining that the symbols are part of an outgoing data block;
• calculating error correcting code for the symbols based on a bit size for the error correcting code and a number of lanes for transmission of the data block;
• augmenting each lane of the data block with error correcting code;
• and
• transmitting the data block across a multi-lane link;
• further comprising preparing the data block for transmission without including bits to represent synchronization header (sync hdr) information.

One or more non-transitory computer-readable media comprising instructions to cause an apparatus, upon execution of the instructions by one or more processors of the apparatus, to:

• receive, at a port, one or more outgoing symbols for transmission;
• determine that the symbols are part of an outgoing data block;
• calculate error correcting code for the symbols based on a bit size for the error correcting code and a number of lanes for transmission of the data block;
• augment each lane of the data block with error correcting code;
• and
• transmit the data block across a multi-lane link;
• the instructions to cause the apparatus to prepare the data block for transmission without including bits to represent synchronization header (sync hdr) information and add in the data block a start data stream ordered set (SDS OS), the SDS OS indicating a start of a data stream to replace the sync hdr.

A system comprising:

• a host device comprising a downstream port, the downstream port to:
• receive, at the downstream port, one or more outgoing symbols for transmission,
• determine that the symbols are part of an outgoing data block,
• calculate error correcting code for the symbols based on a bit size for the error correcting code and a number of lanes for transmission of the data block,
• prepare the data block for transmission without including bits to represent synchronization header (sync hdr) information,
• add a start data stream ordered set (SDS OS) in the data block for transmission, the SDS OS indicating a start of a data stream to replace the sync hdr,
• augment each lane of the data block with error correcting code, and
• transmit the data block across a multi-lane link;
• and
• an endpoint device comprising an upstream port coupled to the downstream port across the multi-lane link, the upstream port to:
• receive the data block from the downstream port across the multi-lane link;
• determine a start of the data block based on the SDS OS in the data block;
• identify error correcting code from error correcting code bits received on each lane of the data block;
• determine errors in the data block based on the error correcting code;
• and
• correct one or more received data symbols in the data block based on a determined error and the error correcting code.