Double data rate interpolating analog to digital converter
AssigneeHuawei Technologies Co., Ltd.
InventorKimmo Koli
Life of this patent
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Abstract
A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core, and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.
Claims20
A double data rate comparator device, comprising:
- a double data rate comparator core configured to compare a voltage of an input signal (IN) to a reference signal (REFN) during each of a rising edge and a falling edge in a single clock cycle of a clock input (CLK) to the double data rate comparator core, wherein the double data rate comparator core comprises a p-type metal-oxide-semiconductor (PMOS) differential amplifier stage and an n-type metal-oxide-semiconductor (NMOS) differential amplifier stage connected together in a push-pull configuration;
- and
- a double data rate set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle, wherein the double data rate set-reset flip flop circuit comprises:
- a set input (S);
- and
- a reset input (R) connected to respective outputs (PN, MN) of the double data rate comparator core.
A radio receiver comprising:
- a double data rate comparator device, comprising:
- a double data rate comparator core configured to compare a voltage of an input signal (IN) to a reference signal (REFN) during each of a rising edge and a falling edge in a single clock cycle of a clock input (CLK) to the double data rate comparator core, wherein the double data rate comparator core comprises a p-type metal-oxide-semiconductor (PMOS) differential amplifier stage and a n-type metal-oxide-semiconductor (NMOS) differential amplifier stage connected together in a push-pull configuration;
- and
- a double data rate set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle, wherein the double data rate set-reset flip flop circuit comprises:
- a set input (S);
- and
- a reset input (R) connected to respective outputs (PN, MN) of the double data rate comparator core.
A double data rate interpolating analog-to-digital converter comprising:
- a first double data rate comparator device;
- a second double data rate comparator device;
- and
- a first two-stage interpolator block, comprising:
- a first stage comprising a double data rate time-based interpolator block configured to:
- receive a first lower input signal and a first upper input signal, wherein the first lower input signal is connected to one of a minus output or a plus output of the first double data rate comparator device, and the first upper input signal is connected to a corresponding one of a minus output or a plus output of the second double data rate comparator device;
- and
- produce an interpolator output signal, wherein a slope change of the interpolator output signal is linearly related to a timing between the first lower input signal and the first upper input signal;
- and
- a second stage comprising a first plurality of complementary metal-oxide-semiconductor (CMOS) inverters, wherein each CMOS inverter is configured to:
- receive the interpolator output signal;
- and
- produce a delayed inverter output signal.
Dependencies are inferred from the claim text.