Circuitry for low input charge analog to digital conversion

An input circuit for an analog to digital converter, the input circuit comprising:

• a first channel selection switch that closes to connect a first analog input node to an intermediate node to thereby charge the intermediate node to a voltage at the first analog input node, the first channel selection switch being closed during a first period of time beginning in response to a start of a sampling cycle of the analog to digital converter;
• a capacitive node connected to an output node;
• discharge circuitry connected between the first channel selection switch and the output node and configured to discharge the capacitive node during the first period of time;
• level shifting circuitry configured to charge the capacitive node to a voltage at the intermediate node less a threshold voltage of a first transistor of the level shifting circuitry during a second period of time beginning in response to expiration of the first period of time;
• and
• a selection switch that closes to connect the intermediate node to the output node to thereby charge the output node to the voltage at the intermediate node, the selection switch being closed in response to expiration of the second period of time;
• wherein the selection switch opens to disconnect the intermediate node from the output node at an end of the sampling cycle of the analog to digital converter.

An input circuit for an analog to digital converter, the input circuit comprising:

• a first channel selection switch that closes to connect a first analog input node to an intermediate node to thereby charge the intermediate node to a voltage at the first analog input node, the first channel selection switch being closed during a first period of time beginning in response to a start of a sampling cycle of the analog to digital converter;
• a capacitive node connected to an output node;
• charge circuitry connected between the first channel selection switch and the output node and configured to charge the capacitive node to a supply voltage during the first period of time;
• level shifting circuitry configured to discharge the capacitive node to a voltage at the intermediate node plus a threshold voltage of a first transistor of the level shifting circuitry during a second period of time beginning in response to expiration of the first period of time;
• and
• a selection switch that closes to connect the intermediate node to the output node to thereby discharge the output node to the voltage at the intermediate node, the selection switch being closed in response to expiration of the second period of time;
• wherein the selection switch opens to disconnect the intermediate node from the output node at an end of the sampling cycle of the analog to digital converter.

An input circuit for an analog to digital converter, the input circuit comprising:

• a first channel selection switch that closes to connect a first analog input node to an intermediate node to thereby charge the intermediate node to a voltage at the first analog input node, the first channel selection switch being closed during a first period of time beginning in response to a start of a sampling cycle of the analog to digital converter;
• a capacitive node connected to an output node;
• a first control circuit connected between the first channel selection switch and the output node and configured to set a charge at the capacitive node to a desired voltage during the first period of time;
• a second control circuit configured to set a charge at the capacitive node to a voltage at the intermediate node, modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor connected to the intermediate node and a second transistor connected to the output node, during a second period of time beginning in response to expiration of the first period of time;
• and
• a selection switch that closes to connect the intermediate node to the output node to thereby charge the output node to the voltage at the intermediate node, the selection switch being closed in response to expiration of the second period of time;
• wherein the selection switch opens to disconnect the intermediate node from the output node at an end of the sampling cycle of the analog to digital converter.