Multi-core circuit with mixed signaling

A mixed signaling lab-on-a-chip, comprising:

• a set of enterprise class central processing unit (CPU) cores coupled via an inter-core link;
• a set of analog circuits having an analog input, each analog circuit coupled to a respective CPU core, and including a digital to analog (D/A) converter coupled via a separate private bus to the respective CPU core;
• a set of extra D/A converters coupled to a supervisory CPU core via another separate private bus;
• a field programmable gate array (FPGA) control circuit coupled to the inter-core link and the set of analog circuits to provide a predictable clock timing to the set of analog circuits and control signals to the set of CPU cores;
• a field programmable analog array (FPAA) coupled to the inter-core link and having inputs coupled to the set of D/A converters and at least one output coupled to the analog input;
• and
• an analog to digital module in at least one CPU core that includes instructions to perform an analog to digital (A/D) conversion to create digital representation of the analog input using the predictable clock timing and control signals from the FPGA.