Analog-to-digital and digital-to-analog converter, related integrated circuit, electronic system and method

A converter circuit configured to selectively convert an analog input voltage into a digital output signal or a digital input signal into an analog output voltage as a function of a mode signal;

• wherein the converter circuit comprises a timer circuit, a ramp generator and a control circuit;
• wherein the control circuit is configured to generate a start-of-conversion signal;
• wherein the ramp generator is configured to:
• monitor the start-of-conversion signal, and once the start-of-conversion signal is set:
• when the mode signal indicates an analog-to-digital conversion, generate a timer stop signal via a variation of at least one ramp signal and a comparator after a time interval determined as a function of a value of the analog input voltage, thereby implementing an analog-to-time conversion;
• and
• when the mode signal indicates a digital-to-analog conversion, vary the at least one ramp signal until a ramp stop signal is set and, in response to the ramp stop signal, determine the analog output voltage as a function of the at least one ramp signal, thereby implementing a time-to-analog conversion;
• wherein the timer circuit is configured to:
• monitor the start-of-conversion signal, and once the start-of-conversion signal is set:
• when the mode signal indicates an analog-to-digital conversion, vary at least one count value until the timer stop signal is set and, in response to the timer stop signal, determine the digital output signal as a function of the at least one count value, thereby implementing a time-to-digital conversion;
• when the mode signal indicates a digital-to-analog conversion, generate the ramp stop signal by varying the at least one count value after a time interval determined as a function of a value of the digital input signal, thereby implementing a digital-to-time conversion;
• wherein the timer circuit comprises at least one counter providing the at least one count value, and a ring oscillator comprising a first delay stage, a plurality of intermediate delay stages and a last delay stage;
• wherein each delay stage of the ring oscillator comprises:
• an input terminal and an output terminal, the input terminal of each intermediate delay stage being connected to the output terminal of an upstream delay stage, the output terminal of each intermediate delay stage being connected to the input terminal of a downstream delay stage, wherein the output terminal of the last delay stage is connected to the input terminal of the first delay stage, and wherein the signal at the output terminal of the last delay stage corresponds to a clock signal used to increase the at least one counter;
• and
• a set-reset latch having a set terminal, a reset terminal and an output terminal, wherein the set terminal of the set-reset latch is connected to the input terminal of the respective delay stage, the reset terminal of the set-reset latch is connected to the output terminal of a downstream delay stage and the output terminal of the set-reset latch is connected to the output terminal of the respective delay stage;
• wherein the timer circuit is configured to:
• when the mode signal indicates an analog-to-digital conversion:
• reset the set-reset latches of the delay stages of the ring oscillator and reset the at least one count value of the at least one counter;
• in response to the start-of-conversion signal, start the ring oscillator by setting the set-reset latch of the first delay stage;
• in response to the timer stop signal, stop the ring oscillator;
• determine the digital output signal as a function of the at least one count value provided by the at least one counter and the signals at the output terminals of the set-reset latches;
• and
• when the mode signal indicates a digital-to-analog conversion:
• reset the set-reset latches of the delay stages of the ring oscillator and set the at least one count value of the at least one counter to a respective value determined as a function of the digital input signal;
• in response to the start-of-conversion signal, start the ring oscillator by setting the set-reset latch of a delay stage selected amongst the delay stages of the ring oscillator as a function of the digital input signal;
• compare the at least one count value of the at least one counter with a reference value;
• and
• in response to the comparison, generate the ramp stop signal when the at least one count value of the at least one counter reaches the reference value.

A method of selectively converting an analog input voltage into a digital output signal or a digital input signal into an analog output voltage as a function of a mode signal, the method comprising:

• receiving the mode signal at a first time to indicate an analog-to-digital conversion;
• receiving the analog input voltage;
• in response to the mode signal indicating the analog-to-digital conversion, generating a timer stop signal based on a ramp signal after a time interval determined as a function of a value of the analog input voltage;
• varying a count value until the timer stop signal is set;
• determining the digital output signal as a function of the count value when the timer stop signal is set;
• receiving the mode signal at a second time to indicate a digital-to-analog conversion;
• receiving the digital input signal;
• in response to the mode signal indicating digital-to-analog conversion, generating a ramp stop signal by varying the count value after a time interval determined as a function of a value of the digital input signal;
• varying the ramp signal until the ramp stop signal is set;
• and
• in response to the ramp stop signal, determining the analog output voltage as a function of the ramp signal.